1. Field
The technology described herein relates to attenuators.
2. Discussion of Related Art
Attenuators are devices, sometimes implemented as circuits, which provide an output signal that is attenuated relative to a corresponding input signal. For instance, an input signal having an initial energy may be input to an attenuator, which then outputs an output signal having an attenuated energy relative to the initial energy. Attenuators may be useful in any system or circuit that requires control of signal gain, such as communications systems, medical devices, cellular telephone base stations, industrial instruments, and consumer electronics, to name a few.
Integrated circuit (IC) attenuators can be formed in various materials, and are sometimes formed in compound semiconductor materials, such as gallium arsenide (GaAs). The properties of a given material, such as GaAs, may influence the design of the integrated circuit attenuator implemented in the material. For example, integrated circuit attenuators may implement one or more transistors, as passive components or otherwise. Transistors made in GaAs are typically depletion mode transistors, and thus have a negative threshold voltage VTH, also referred to as the pinch-off voltage Vp. To use depletion mode transistors as passive components (e.g., variable resistors) thus requires the ability to have a negative control voltage, i.e., a negative gate-to-source (Vgs) voltage. However, IC attenuators are often implemented in an environment (e.g., a larger circuit) for which the standard supply voltages are positive. Thus, design of an IC attenuator in some types of materials may reflect the contrast between a need for a negative control voltage for some components and the lack of a negative supply voltage.
FIG. 1 illustrates a conventional π-type voltage-controlled variable attenuator which can be implemented as an IC in GaAs, and which allows for control of the depletion mode field effect transistors (FETs) using positive voltages. The attenuator 100 has a series arm including two field effect transistors, FET1 and FET2. The source of FET1 is coupled to the drain of FET2. The attenuator input AC Input is provided to DC block capacitor C101, which is coupled to the drain of FET1. The signal transmitted along the series arm of attenuator 100 passes from FET2 to DC block capacitor C102, which is coupled to the source of FET2. The attenuator output AC Output is provided by DC block capacitor C102.
The attenuator 100, being a π-type attenuator, includes two shunt arms coupled to the series arm, which provide impedance matching of the attenuator with other components and/or circuits to which the attenuator may be coupled. The first shunt arm includes DC block capacitor C103, FET3, and DC block capacitor C105, which is coupled to ground. The second shunt arm includes DC block capacitor C104, FET4, and DC block capacitor C106, which is coupled to ground. As shown, the attenuator 100 also includes multiple resistors (R101-R107), described more fully below.
Broadly speaking, the attenuator 100 provides a variable amount of attenuation of input signal AC Input, ranging from a small degree, or amount, of attenuation to a large degree of attenuation. The degree of attenuation is determined by the interaction, and more specifically the resistances, of the series and shunt arms, and thus by the bias conditions of the FETs, described more fully below. In attenuator 100, the resistance of the series arm generally moves in an opposite direction from that of the shunt arms. When the resistance of the shunt arms is large, the resistance of the series arm is small, and the output signal AC Output is only slightly attenuated compared to the input signal AC Input. If the resistance of the series arm is large, the resistance of the shunt arms is small, and AC Output is significantly attenuated compared to AC Input.
A more detailed understanding of the operation of attenuator 100 can be gained by considering the various operating states of the FETs. The FETs are depletion mode transistors (meaning they have a negative threshold, or pinch-off, voltage) and are configured as passive components (i.e., variable resistors). There are three operating states for each transistor to consider:Vgs≧0   State 1VTH≦Vgs<0   State 2Vgs<VTH   State 3where Vgs is the gate-to-source voltage of the transistor and VTH is the threshold voltage of the transistor. In State 1, Vgs≧0, the transistor is fully ON (conducting), meaning its resistance is approximately zero, and thus it operates as a short circuit. In State 2, VTH≦Vgs<0, the transistor is ON and has a variable resistance that depends on the value of Vgs. State 2 is the linear region of operation. In State 3, Vgs<VTH, the transistor is OFF, meaning it has an approximately infinite resistance and operates like an open circuit.
With that background, the operation of attenuator 100 can be understood in detail. As mentioned, the attenuator 100 provides a variable degree of attenuation of the input signal AC Input depending on the resistances of the series and shunt arms. As explained, the resistance of each FET in attenuator 100 depends on the voltage potentials at the gate and body (i.e., source and drain), also referred to as the bias condition, of that FET. In attenuator 100, these voltages depend on the relative values of Vref and Vctrl.
The voltage Vref is a positive constant voltage, and is applied to node 103 through resistor R101. The bodies of FET1 and FET2 (i.e., nodes 101, 102, and 103) all have voltages approximately equal to the value of Vref because of the presence of DC block capacitors C101, C102, C103, and C104, which provide some isolation of FET1 and FET2 from the rest of the attenuator. The voltage potentials at the gate of FET1 (node 104) and the gate of FET2 (node 109) are controlled by Vctrl, a variable voltage source having positive voltage values. Vctrl is applied to nodes 104 and 109 through resistors R102 and R103, respectively. Thus, the gate-to-source voltages Vgs for FET1 and FET2 (approximately equal to the gate-to-drain voltage Vgd in this configuration) are both approximately given by: Vgs=Vgd=Vctrl−Vref. By varying Vctrl between 0 Volts as a lower limit and approximately Vref as an upper limit, Vgs (and Vgd) for FET1 and FET2 will vary from approximately −Vref to approximately zero. Therefore, the resistance values of FET1 and FET2 can be controlled. Moreover, if Vref is greater than or equal to the absolute value of the threshold voltage VTH of the FETs, all three operating states of transistors FET1 and FET2, described above, can be achieved.
Meanwhile, the voltage potential at the drains and sources of FET3 and FET4, i.e., nodes 105, 106, 108, and 111, are controlled by the variable voltage Vctrl. As shown, Vctrl is applied to node 105 through resistor RI 04, and to node 106 through resistor R105. The gate terminals of FET3 and FET4 (i.e., nodes 107 and 110) are coupled to ground through resistors R106 and R107, respectively. Thus, Vgs and Vgd for FET3 and FET4 are approximately given by: Vgs=Vgd=−Vctrl. By varying Vctrl from approximately 0 Volts as a lower limit to approximately Vref as an upper limit, Vgs (and Vgd) for FET3 and FET4 will vary from approximately 0 Volts to −Vref. Therefore, the resistance values of FET3 and FET4 can be controlled. Moreover, if Vref is greater than or equal to the absolute value of the threshold voltage VTH of the FETs, all three operating states of transistors FET3 and FET4, described above, can be achieved.
Several aspects of the design and operation of attenuator 100 can be noted. While Vgs for FET1 and FET2 varies from approximately zero to −Vref, the value of Vgs for FET3 and FET4 is varying from −Vref to zero. Therefore, FET1 and FET2 will display decreasing resistances when FET3 and FET4 display increasing resistances, and vice versa. The presence of DC block capacitors C103 and C104 provides some degree of isolation of the series arm from the shunt arms, and thus enables the opposing behavior of the resistances of the series and shunt arms in attenuator 100. Moreover, at least some of the nodes of the attenuator (e.g., nodes 101, 102, and 103) maintain an approximately constant voltage during operation, while the nodes at the bodies of the FETs in the shunt arms (e.g., nodes 105, 106, 108, and 111) experience a varying voltage during operation.
FIG. 2 shows the small signal equivalent of attenuator 100 in FIG. 1. In circuit 200, each transistor FETn (n is the index of the transistor, i.e., n=1, 2, 3, or 4), is simplified to be a resistance RFETn in parallel with a capacitance CFETn. Both RFETn and CFETn vary according to the bias condition (i.e., the value of Vgs) of the corresponding transistor. When Vctrl is 0 Volts, as described above, FET1 and FET2 are biased to be in the OFF-state (assuming the absolute value of Vref is greater than the absolute value of VTH), and FET3 and FET4 are in the ON-state. Thus, RFET1 and RFET2 approach their maximum values while RFET3 and RFET4 approach their minimum values. In this state, the attenuator provides the maximum loss (i.e., maximum attenuation) to the AC Input signal. When Vctrl is set to Vref, FET1 and FET2 are in the ON-state and FET3 and FET4 in the OFF-state. Thus, RFET1 and RFET2 approach their minimum values, while RFET3 and RFET4 approach their maximum values. In this state, the attenuation level of AC Input approaches its minimum value. When Vctrl is set between 0 Volts and Vref, the π-type resistor network provides an attenuation level varying between its maximum and minimum values, thus realizing an analog variable attenuator. Resistors R101, R104, and R105 have large resistance values relative to the variable resistances RFETn, and therefore have less influence on the performance of the attenuator.